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23.3.2 Response Time
There is a delay from when the actual input voltage changes polarity, to when the output toggles. This
period is called the response time and can be altered by increasing or decreasing the bias current to the
comparator through the BIASPROG, FULLBIAS and HALFBIAS fields in the ACMPn_CTRL register, as
described in Table 23.1 (p. 324) .Setting the HALFBIAS bit in ACMPn_CTRL effectively halves the
current as observed in Table 23.1 (p. 324) . Setting a lower bias current will result in lower power
consumption, but a longer response time.
If the FULLBIAS bit is set, the highest hysteresis level should be used to avoid glitches on the output.
Table 23.1. Bias Configuration
BIASPROG
Bias Current (μA)
FULLBIAS=0,
HALFBIAS=1
FULLBIAS=0,
HALFBIAS=0
FULLBIAS=1,
HALFBIAS=1
FULLBIAS=1,
HALFBIAS=0
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
0b1101
0b1110
0b1111
0.05
0.1
0.2
0.3
0.4
0.5
0.6
0.7
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.3
6.5
13
20
26
33
39
46
65
72
78
85
91
98
104
111
6.5
13
26
39
52
65
78
91
130
143
156
169
182
195
208
221
23.3.3 Hysteresis
In the analog comparator, hysteresis can be configured to 8 different levels, including off which is level
0, through the HYSTSEL field in ACMPn_CTRL. When the hysteresis level is set above 0, the digital
output will not toggle until the positive input voltage is at a voltage equal to the hysteresis level above
or below the negative input voltage (see Figure 23.2 (p. 325) ). This feature can be used to filter out
uninteresting input fluctuations around zero and only show changes that are big enough to breach the
hysteresis threshold.
2011-04-12 - d0001_Rev1.10
324
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